Carbon nanotube research concluded

The European projects ‘Carbon nanotubes technology on Si IC’s’ and ‘Nanowire-based one-dimensional electronics’ have been completed.

The results of CARBonCHIP form the baseline for technological assessment of carbon nanotubes and provide realistic routes for CNT development.

Within the NODE project, the development of growth and processing technologies for semiconductor nanowire devices has ultimately led to the demonstration of first functional nanowire field effect transistors.

Imec participated in both projects and was coordinator of the CARBonCHIP project.

The CARBonCHIP project addresses the potential of integrated CNT technology. An important realisation has been the development of a process flow for the integration of horizontal and vertical CNTs on patterned Si.

The impact of these results is most clearly illustrated by the construction of a material-based roadmap for integrating CNTs in back-end-of-line and front-end-of-line Si technology. CNTs have remarkable electronic, thermal and mechanical properties and can be grown by a bottom-up process.

They can potentially extend Moore’s law towards 2020 and beyond.

The process flow could be developed after thorough investigations of the catalysis and growth of CNTs. Since CNT growth is a catalytic process, the deposition of the catalyst nanoparticles is a critical step in CNT growth.

Within the project, three main routes for developing catalysts and subsequent CNT growth have been developed, including a novel metal nanoparticle (eg, Ni) catalyst deposition technique using electrochemistry (electrochemical deposition or ECD), nanotube formation in large-pore zeolites and the grafting of nanoparticles as a technology for depositing ex-situ grown CNTs.

Subsequently, the different growth processes and selected catalysts have been used to guide a process flow for the integration of horizontal and vertical CNTs on patterned Si.

Chemical vapour deposition was identified as the most promising technique for CNT integration. The project partners have integrated dense materials composed of 4 nm diameter tubes (estimated density of tubes in the bundles close to 4x1012cm^-2), grown inside via holes down to 140 nm in diameter.

Integrations have been performed on two different materials with metal being either Si or TiN. The integration on Si may be relevant for the first level of interconnects on the source and drain of transistors, while integration on TiN can be relevant for CNT vias on copper or other metal lines.

In particular for interconnects, a full 200 mm integration flow for CNTs, selectively grown into contact holes using Ni catalysts, could be demonstrated.

As a main outcome of the NODE project, different nanowire transistor concepts have been designed, fabricated and characterised. A selection of concepts assessed by the project partners contains: a) vertical RF-compatible InAs nanowire transistors; b) steep subthreshold slope devices based on Si nanowires and c) multi-gated Si nanowire Schottky barrier FETs.

The first functional Si nanowire tunnel-FETs processed on 200 mm wafers on a CMOS platform and multi-gated Si nanowire Schottky barrier FETs with inverter function were demonstrated.

With these results, the objectives of the European NODE project have been met. With NODE, the project partners focused on an innovative bottom-up approach to fabricate and integrate nanoelectronic devices, based on self-assembling semiconductor nanowires.

They wanted to investigate their impact as a key add-on technology to standard semiconductor fabrication. Another goal of the project was a deepened understanding of the underlying physics, and the development of new functionalities not found in traditional higher-dimensional device structures.

Much effort was made to realise a CMOS-compatible, large-scale integration of Si-based nanowire devices. All proposed integration schemes have been actively put to test in the 200 mm Si processing facility at IMEC.

To this end, a catalyst-free approach for growing Si and SiGe nanowires onto Si(100) has been developed.

In addition, IMEC developed an integration flow together with the necessary process modules to fabricate vertical nanowire tunnel-FET devices with wraparound gates.

These developments have led to the first large-scale integrated vertical nanowire devices built on a 200 mm wafer platform, with high-k/metal-gate stack.