JTAGLive has introduced a series of debug tools for DSP and microprocessor systems using a variety of RISC and DSP cores.
Using CoreCommander, engineers can activate the OCD (on-chip debug) modes of a range of cores to affect ‘kernel-centric’ testing.
While many devices are now equipped with JTAG (IEEE Std. 1149.1) boundary-scan registers (BSRs), which are used extensively to provide test access into digital and mixed-signal designs, some microprocessors and DSPs can be found with deficient or even non-existent boundary-scan test registers.
CoreCommander routines are suitable for diagnosing faults on ‘dead-kernel’ boards in either design debug or repair, since no on-board code is required to set memory reads and writes. Boundary-scan deficient parts can also be better used during production test, as CoreCommander-driven functions increase fault coverage.
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