Improving current flow in ultra-thin semiconductors

Advances in semiconductor manufacturing are enabling ever-thinner chip components, but scaling devices down further can introduce constraints that affect their electrical performance. Now, researchers from POSTECH have resolved this issue by developing a technology that lowers contact resistance by redesigning the metal-semiconductor contact structure in ultra-thin tellurium (Te) transistors. The research findings have been published in ACS Nano.

With the rapid advancement of AI and high-performance computing, the volume of data that semiconductors must process is surging. As a result, the time and energy loss occurring between the ‘logic’ (which handles computations) and ‘memory’ (which stores data) has been identified as a major bottleneck. To address this, 3D integrated structures that stack logic and memory vertically are gaining traction as a next-generation technology. Fabricating these structures requires devices that can operate stably at temperatures below 400°C.

Tellurium is a strong candidate for semiconductor channel material due to its high charge mobility, room-temperature stability and low-temperature processability. However, its narrow band gap makes it prone to ‘leakage current’, where current leaks even when the transistor is turned off. To minimise this, the channel must be fabricated to an ultra-thin thickness of under 5 nanometres (nm) to control electron transport.

When the channel becomes too thin, electron transport across the interface between the metal electrode and the semiconductor becomes severely restricted. A Schottky barrier — an energy barrier that electrons must cross between the metal and semiconductor — grows larger as the channel gets thinner. Ultimately, while researchers could reduce leakage current, doing so simultaneously increased contact resistance, thereby degrading device performance.

To address this, the POSTECH team applied the ‘Raised Source and Drain (RSD)’ structure, a technique conventionally used in silicon processes. The technique deposits additional tellurium to thicken only the areas directly in contact with the electrodes where the current enters and exists (the source and drain). By keeping the current-flowing channel at a thin 4 nm to suppress leakage current while adding extra tellurium to the sections in contact with the metal electrodes, the team allowed the current to flow with improved efficiency.

Experimental results demonstrated that devices utilising this structure experienced a 50-fold reduction in contact resistance, dropping from 97.5 kΩ·μm to 1.7 kΩ·μm. Furthermore, in an extreme environment of -196°C, the on-state current when the device was fully turned on increased by more than 17 times. The team achieved both low resistance and high performance within an ultra-thin structure. This technology can be implemented through a large-area, low-temperature deposition process known as sputtering, ensuring the high scalability required for actual semiconductor mass production.

Professor Byoung Hun Lee from POSTECH’s Department of Electrical Engineering said, “We have broken through the chronic dilemma of ultra-thin semiconductors — where thinner channels traditionally resulted in higher resistance — with a novel band engineering approach called ‘localised thickness control’. We expect this to become a core platform technology that can be widely applied not only to tellurium but also to enhancing the performance of various 2D and ultra-thin semiconductor devices, ultimately accelerating the realisation of next-generation 3D integrated circuits.”

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