XJTAG software for PADS schematic design

The XJTAG software for PADS schematic design significantly increases the design for test and debug capabilities of the schematic capture and PCB design environment.

Printed circuit boards (PCBs) are increasingly densely populated and access to pins under many packages, such as ball grid array (BGA), is virtually impossible. The product was designed to solve the problem of access. Failure to identify and fix design errors at an early stage can result in a board re-spin and a costly delay to a project. DFT Assistant helps validate correct chain connectivity, through full integration with the PADS schematic capture environment.

DFT Assistant comprises two key elements, including the chain checker and the access viewer.

Chain checker identifies common errors in a scan chain, such as incorrectly connected test access ports (TAPs). A single connection error would inhibit an entire scan chain from working. Chain checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.

Access viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets that do not have any JTAG access on the schematic.