Planar CMOS gets a boost

IMEC reports an improved performance for its planar CMOS using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32 nm CMOS node.

The inverter delay advanced from 15 to 10 ps. IMEC also simplified its high-k/metal gate process by decreasing the number of process steps from 15 to 9.

High-performance (low-Vt) high-k/metal-gate CMOS has recently been achieved by applying a thin dielectric cap between the gate dielectric and metal gate. Both gate-first and gate-last integration schemes have proved to be successful.

While the gate-last scheme is now in production for high-performance products, the gate-first option remains attractive for low-cost applications if its complexity can be reduced to the standard CMOS process flow.

One of the possibilities for gate first is a dual-metal dual-dielectric process flow using mostly hard masks to pattern nMOS and pMOS regions selectively.

By applying conventional stress boosters to its gate-first dual-metal dual-dielectric high-k/metal gate CMOS, the organisation has increased the performance of nMOS and pMOS transistors by 16% and 11%. This results in an inverter delay improved from 15 to 10 ps.

For the first time, the compatibility of conventional stress memory techniques with high-k/metal gate has been demonstrated.

IMEC has also simplified the process complexity from dual-metal dual-dielectric to single-metal dual-dielectric by using soft-mask processes and wet removal chemistry.

The process reduces the complexity by 40%, or six steps, compared with dual-metal dual-dielectric. It also allows simpler gate-etch profile control and it offers better prospects for scaling.