'Dirty little secret' threatens Moore's Law

Wednesday, 05 March, 2003

Today's state-of-the-art chips have transistors roughly a micrometre in overall length; dozens of them could perch on top of a human red blood cell.

But this very success has brought the chipmakers to the brink of a steep, new obstacle to further gains in performance.

At the crux of the problem are the tiny metal wires that weave the transistors on chips into integrated circuits. In the most advanced ICs, transistors switch up to 10 billion times a second, and their metal interconnects can barely keep up.

The narrower the wire, the longer it takes a signal to propagate along it.

And each new generation of chips only makes matters worse; while interconnect delay times are stretching out, transistor switching is getting faster, sending more signals down slow lines.

It's the semiconductor industry's dirty little secret, and it threatens the seemingly immutable Moore's Law, namely, that transistor density and hence chip performance will periodically double.

No one knows how a disruption in this prediction would affect the industry; but not many are on record as predicting a happy outcome.

The good news is that the industry thinks it is zeroing in on a solution: change the propagation characteristics of those tiny on-chip transmission lines. But as one might expect, chipmakers are not agreed on a single approach.

Rather, two are on the table, each championed by heavy hitters in the field: Dow Chemical with its spin-on polymer deposition technique, and Applied Materials and Novellus with their chemical vapour deposition-based systems.

Both camps want to decrease the line's capacitance by changing the material that insulates it from the surrounding silicon chip as well as from neighbouring wires.

The capacitance depends on its dielectric constant.

So researchers are developing thin films that have a lower dielectric constant, lower k, than the silicon dioxide insulating layer most commonly used up to now.

The bad news is that these low-k films are extremely difficult to integrate into semiconductor manufacture. They are soft, weak and adhere poorly to both the silicon and the metal wire.

Not nearly as tough as silicon dioxide, they don't stand up to conventional processing but crack and delaminate easily.

As a result, last year low-k dielectrics were used in only a few 130 nm chips. The real action will start later this year, when chipmakers are compelled by the International Technology Roadmap for Semiconductors to start using the new materials in 90 nm chips.

The next generation of 65 nm chips will require even lower-k films that are even more challenging to process.

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