Battery-powered chips could work faster and longer
Researchers at the National University of Singapore (NUS) have invented a novel class of reconfiguration techniques that adaptively extends both the minimum power consumption and the maximum performance of digital circuits, well beyond common voltage scaling. Such extended adaptation allows digital silicon chips to operate at lower power during normal use, and at higher performance level when necessary.
This extends the battery life under uncertain power availability in systems powered by harvesters (eg, solar cells) or rechargeable batteries, while delivering higher peak performance to carry out on-chip data analytics upon the occurrence of events of interest. This is a key enabler for applications such as Internet of Things (IoT), artificial intelligence (AI), wearables and biomedical devices.
Most advanced mobile, IoT and AI applications require a flexible and wide trade-off between the average power (ie, battery life) and the maximum performance that determines system responsiveness (eg, when the screen is touched, or performing data analytics when a sensor produces data of interest). Currently, dynamic voltage scaling is the gold standard in enabling such flexibility.
Operating at voltages around 1 V leads to maximum performance and energy consumption, whereas reduction down to 0.4–0.5 V lowers energy consumption by four to five times and slows the operating speed by nearly 10 times. The drawback of this approach is that voltage scaling generally applies to a fixed digital architecture, although the optimal architecture for energy consumption and performance depends on the adopted voltage.
The NUS invention outperforms voltage scaling since its circuit reconfiguration enables a better match between the architecture and the adopted voltage, and hence further reduction in energy consumption and improvements in performance at different voltages can be achieved. The adaptive digital circuits are able to extend the battery life of intelligent silicon chips by reducing the power consumption under normal use, while scaling up performance to quickly respond to occasional data events.
“Our invention enables reconfiguration of both the ‘data path’, where the actual processing is performed, and the ‘clock path’ that distributes the clock signal to orchestrate the different processing tasks,” said Associate Professor Massimo Alioto, the leader of the NUS Green IC group behind this technological breakthrough. “In both cases, their fundamental building blocks are flexibly merged or split to create the data and clock path structure that improves either energy efficiency or performance at a given voltage.”
Compared to conventional voltage scaling, the approach makes digital circuits more versatile and adaptive, allowing simultaneous optimisation at both ends of the power-performance spectrum. Indeed, the proposed techniques have already led to the demonstration of accelerators and processors with minimal energy consumption.
“Our reconfiguration techniques introduce unprecedented adaptability to fluctuating power availability and performance demand,” said Assoc Prof Alioto. “Compared to the industry-standard voltage scaling technique, measurements on several test chips in our lab have shown that such adaptation extends the battery life of a mobile or wearable device by 1.5 times, while doubling peak performance. Our techniques can also be used to further miniaturise the battery by the same factor, while maintaining the same battery life.
“As further benefit, the power-performance versatility of our circuit techniques allows semiconductor companies to simplify their chip portfolio and reduce the design cost, as the same digital design can be re-used across a wide range of applications and markets.”
The research team is now looking into developing new classes of intelligent silicon systems that allow ultrawide power-performance adaptation in AI accelerators embedded in sensing silicon chips for IoT. This will lead to next-generation systems that are always available, while being able to promptly respond to external events with very significant computational performance.
The team endeavours to enable power-performance adaptation through drop-in techniques and design methodologies in existing system architectures. This allows the achievement of power-performance benefits without disrupting the design ecosystem, thus enabling a rapid and massive adoption of next-generation intelligent systems.
In the meantime, the team has released a technical book to provide the background and details of the silicon chip implementation of processors, accelerators and on-chip memories. An automated design flow has also been created and publicly released over GitHub.
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