Reducing disturbance in next-gen magnetic RAM


Wednesday, 23 March, 2022


Reducing disturbance in next-gen magnetic RAM

SOT-RAM, a promising type of next-generation magnetic memory, could pave the way to ultralow-power electronics. However, scientists from Tokyo University of Science have identified a source of disturbance during the read operation in SOT-RAMs that compromises their reliability. Fortunately, they have also found a method to greatly reduce this disturbance by slightly modifying the SOT-RAM structure.

With the advent of the Internet of Things (IoT) era, many researchers are focused on making most of the technologies involved more sustainable. To reach this target of ‘green IoT’, some of the building blocks of conventional electronics will have to be improved or radically changed to make them not only faster, but also more energy-efficient. In line with this reasoning, many scientists worldwide are currently trying to develop and commercialise a new type of random-access memory (RAM) that will enable ultralow-power electronics: magnetic RAM.

Each memory cell in a magnetic RAM stores either a ‘1’ or a ‘0’ depending on the magnetic orientation of the two magnetic layers. Various types of magnetic RAM exist, and they mainly differ in how they modify the magnetic orientation of the magnetic layers when writing to a memory cell. In particular, spin injection torque RAM, or STT-RAM, is one type of magnetic memory that is already being commercialised. However, to achieve even lower write currents and higher reliability, a new type of magnetic memory called spin orbit torque RAM (SOT-RAM) is being actively researched.

In SOT-RAM, by leveraging spin-orbit interactions, the write current can be immensely reduced, which lowers power consumption. Moreover, since the memory readout and write current paths are different, researchers initially thought that the potential disturbances on the stored values would also be small when either reading or writing. Unfortunately, this turned out not to be the case.

In 2017, in a study led by Professor Takayuki Kawahara of the Tokyo University of Science, researchers reported that SOT-RAMs face an additional source of disturbance when reading a stored value. In conventional SOT-RAMs, the readout current actually shares part of the path of the write current. When reading a value, the readout operation generates unbalanced spin currents due to the spin Hall effect. This can unintentionally flip the stored bit if the effect is large enough, making reading in SOT-RAMs less reliable.

To address this problem, Prof Kawahara and colleagues conducted another study, which was published in the journal IEEE Transactions on Magnetics. The team came up with a new reading method for SOT-RAMs that can nullify this new source of readout disturbance. In short, their idea is to alter the original SOT-RAM structure to create a bidirectional read path. When reading a value, the read current flows out of the magnetic layers in two opposite directions simultaneously. In turn, the disturbances produced by the spin currents generated on each side end up cancelling each other out.

In addition to cementing the theory behind this new source of readout disturbance, the researchers conducted a series of simulations to verify the effectiveness of their proposed method. They tested three different types of ferromagnetic materials for the magnetic layers and various device shapes, with favourable results.

“We confirmed that the proposed method reduces the readout disturbance by at least 10 times for all material parameters and device geometries compared with the conventional read path in SOT-RAM,” Prof Kawahara said.

To top things off, the research team checked the performance of their method in the type of realistic array structure that would be used in an actual SOT-RAM. This test is important because the read paths in an array structure would not be perfectly balanced depending on each memory cell’s position. The results show that a sufficient readout disturbance reduction is possible even when connecting about 1000 memory cells together.

The team is now working towards improving their method to reach a higher number of integrated cells. They say their study could pave the way towards a new era in low-power electronics, from personal computers and portable devices to large-scale servers.

“We expect next-generation SOT-RAMs to employ write currents an order of magnitude lower than current STT-RAMs, resulting in significant power savings,” Prof Kawahara said. “The results of our work will help solve one of the inherent problems of SOT-RAMs, which will be essential for their commercialisation.”

Image credit: ©stock.adobe.com/au/LariBat

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