Signal analysis downconverter

RF Engines has been contracted by Eonic of Delft in the Netherlands to develop a digital downconverter to be used in a signal processing platform.

The high-speed design will enable the real-time extraction of large sections of spectrum from a wideband signal for subsequent analysis. The Eonic specification requires particularly demanding channel passband, stopband, ripple and spurious-free dynamic range (SFDR) performance, as well as requiring a complex range of parallelisms (levels of de-multiplexing) to enable the multiple outputs to precisely match the required data rates.

The RFEL core is to be implemented in a single Altera Stratix III FPGA and then incorporated into Eonic's bespoke hardware. It will accept data from a MAX109 analog to digital converter running at speeds of up to 2.2 giga samples per second.

The design will incorporate the required functions, including mixers, half-band-filters and down-samplers, in a flexible architecture that will provide all the required functionality for both baseband and IF input signals.

The high flexibility and decimation data rate of the specification make the implementation and the routing/placing constraints particularly demanding and require the design of a novel, parallel down-sampler that is specifically tailored to the Stratix III silicon architecture.

The outputs of the core will also be selectable from various nodes within the core to enable the full range of required decimation rates to be achieved.