Termination regulator

Texas Instruments has introduced a sink/source double data rate termination regulator that supports all power management requirements for DDR, DDR2, DDR3 and DDR4 low-power memory termination.

The regulator requires only 20 µF of ceramic output capacitance, nearly 80% less than other solutions.

The wide-bandwidth internal transconductance, Gm amplifier and integral dynamic voltage positioning enables ultra-fast transient ability with minimal external output capacitance.

In a typical application with a -1.5 to +1.5 A load step, the output voltage variation is less than 25 mV. The device is designed to work with bias voltage between 2.375 and 3.5, which makes it suitable for systems where only a 2.5 or 3.3 V rail is available. Additionally, the device includes the S3 sleep-state control during suspend to RAM.

The regulator can also be used as a general-purpose, high-performance low dropout regulator with an input range of 1.1 to 3.5 V. The device supports tracking start-up and shutdown features when the enable pin is connected to the system bus voltage, which simplifies the design process by allowing the designer to easily implement sequencing in multi-rail systems.