MathWorks Vision HDL Toolbox R2019b

MathWorks has announced that with the availability of Release 2019b of the MATLAB and Simulink product families, Vision HDL Toolbox includes native multipixel streaming support to process high-frame-rate (HFR) and high-resolution videos on FPGAs. Video, image processing and FPGA design engineers can speed the exploration and simulation of behaviour and implementation trade-offs when processing 4k or 8k video and videos with resolutions of 240 fps or higher.

Engineers designing FPGAs for real-time processing of high-resolution and HFR video in applications such as industrial inspection, medical imaging and intelligence, surveillance and reconnaissance (ISR) are challenged to meet throughput, resource usage and power consumption targets. The toolbox offers blocks that can process four or eight pixels in parallel, with the underlying hardware implementation automatically updated to support simulation and code generation with the specified parallelism.

This capability helps hardware engineers collaborate with image and video processing engineers to explore and simulate vision processing hardware behaviour at a high level of abstraction. By adding HDL Coder to this design workflow, engineers can generate synthesisable, optimised target-independent VHDL or Verilog code directly from their verified high-level models.

The product provides pixel-streaming algorithms for the design and implementation of vision systems on FPGA, ASIC and SoC devices. It provides a design framework that supports a diverse set of interface types, frame sizes and frame rates. The video and image processing algorithms in the toolbox model hardware implementations include latency, control signals and line buffers. The algorithms are designed to generate readable, synthesisable code in VHDL and Verilog (with HDL Coder). The generated HDL code is FPGA-proven for frame sizes up to 8k resolution and for HFR video.