Sub-32-nm CMOS research partnership

Powerchip Semiconductor Corporation (PSC) has entered into a partnership with IMEC to perform research and development for the sub-32-nm memory process generations.

As part of the agreement, PSC will collaborate within IMEC’s advanced lithography program addressing immersion, double patterning and EUV lithography challenges.

PSC researchers will reside at IMEC to closely collaborate with IMEC’s researchers. In this way, the team will build up fundamental understanding and develop robust solutions for the 32 nm and beyond memory process generations.

Powerchip Semiconductor Chairman Dr Frank Huang said, “As photolithography technology approaches 32 nm we encounter physical limitations while at the same time development costs are increasing. Therefore the trend of alliances and joint development will become more and more prominent in the industry.”