Wire Shrinking

Infineon Technologies has announced that present techniques for integrated circuit wiring can be used for future chip generations, extending to the 2011-2014 timeframe.

Infineon researchers have produced metal lines, at a width of 40 to 50 nm, embedded in the grooves of a dielectric film used for electrical isolation. Such narrow metal lines are used for the shortest electrical connections between the transistors in the chip.

Lithography tools needed for the fabrication of future chip generations in the 2011-2014 timeframe do not yet exist. Infineon overcame this issue by using a spacer technique to narrow the mask openings for pattern transfer into the dielectric film.

The results from research demonstrate that today's wiring technology can be used through the end of the International Technology Roadmap for Semiconductors (ITRS), which extends to 2014.