Actel has introduced its Libero version 6.2 Integrated Design Environment (IDE), which integrates design tools to enable FPGA designers to achieve high results in terms of quality, efficiency and functionality.
With Libero 6.2, the company unveils its SmartTime static timing analysis environment, enabling users to analyse and manage timing constraints, perform timing verification, and ensure predictable timing closure through a tight integration with timing-driven place and route.
Actel and Mentor have extended their partnership to provide Mentor Graphics' ModelSim AE simulation as an integral part of the Libero 'Gold' package, which is now free to all Actel users.
In addition, the 6.2 IDE includes enhanced synthesis capabilities from Synplicity and physical synthesis features from Magma Design Automation and runs on Linux and Solaris platforms.
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