Clarke & Severn STC5420 timing chip

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The RoHS 6/6 compliant STC5420 series is a single-chip clock synchronisation solution for applications in SDH/SETS, SONET and synchronous ethernet network elements. The devices are fully compliant with ITU-T G.813 option one and two and Telcordia GR1244 and GR253.

The series accepts 12 clock reference inputs from 8 kHz to 125 MHz in LVPECL, LVCMOS or LVDS and generates 10 synchronised clock outputs from 2 kHz to 312.5 MHz in LVCMOS, LVPECL or LVDS. The synchronised outputs may be programmed for a wide variety of frequencies including Nx8 kHz, OC-n, ethernet frequencies and framing pulse clocks. Reference inputs are individually monitored for activity and quality. Reference selection may be manual, fast-manual or automatic.

Independent timing generators operate in freerun, synchronised, pseudo-holdover and holdover mode. Each timing generator includes a DSP-based PLL. SDP-based PLL technology removes the need for any external parts except the 12.8 MHz oscillator and provides good performance and reliability for the models.

Within the STC5420 product range, a smaller TQ64 package configuration option is available as well as part number configurations that allow for reduced functionality and lower cost.

Features include: master/slave and multiple master redundant applications; seven clock synthesisers generate frequencies: 1xOC-N, x1 ethernet, x4 general purpose, x1 framing pulse; programmable compensation for phase delay between master and slave unit in 0.1 ns steps; phase align or hitless reference locking/switching; programmable loop bandwidth from 0.1 to 100 Hz; programmable phase skew in synthesiser level; supports bus interface: Intel, Motorola, Multiplex, SPI; single 3.3 V operation.