Digital data buffering

AverLogic Technologies has introduced its high-performance FIFO (first-in-first-out) field memory chips designed to buffer audio/video/graphic digital data for a wide range of applications.

These include video capture or video editing systems for NTSC/PAL or SVGA resolution, security systems, scan rate converter, PIP (picture in picture) video display, timing correction, format conversion, multimedia systems, buffer for communication system and DTV/HDTV video stream buffer.

The AL440B FIFO memory provides independent 8-bit input and output ports that can operate at a maximum speed of 80 MHz. The built-in address and pointer control circuits provide a straightforward bus interface to serially read/write memory that can reduce inter-chip design efforts.

Manufactured using an embedded high-density memory cell array, the device uses process technologies with extended controller functions (write mask, read skip, window mode read/write) allowing easy operation of non-linearity and regional read/write FIFO for PIP, digital TV, security system and video camera applications. Expanding the data bus width is also possible using multiple chips in parallel.

The 4 Mb AL 440B is configured as 512 K x 8-bit FIFO to accommodate NTSC,PAL or up to SVGA resolution. Running at high speed (80 MHz maximum) and low power consumption AC characteristics (3.3 V power supply) allow the performance and quality application capability for designs such as HDTV.

The AL422B consists of 3 Mb of DRAM, and is configured as 380 K x 8-bit FIFO. The high speed and low power consumption are achieved by using 0.35 µm process with embedded EDO dynamic memory. The interface is user friendly since all complicated DRAM operations are already managed by the internal DRAM controller. The device can accept either 3.3 or 5 V power with slightly different external configuration.