Semiconductor protection tips for 3-level topologies

Supplied by Semikron Pty Ltd on Monday, 21 October, 2019


3-level topologies are mainly used in UPS and solar applications due to their high efficiency and low harmonic distortion of the grid. Essential for the design of the driver is to limit the voltage at the IGBT and handling of short circuits.

This application note describes the control and protection of power semiconductors in 3-level NPC and TNPC topologies.

Related White Papers

How to design rapid-start power applications that never fail

Learn how to design an isolated power system that can start up within 10 ms of application of...

Your guide to high performance power module packaging

Examine the key attributes of power module packaging. Learn how to deliver your...

Factorised Power Architecture — achieving high density and efficiency in board-mounted power

Solving today's high-current and high-density point-of-load (PoL) problems requires a...


  • All content Copyright © 2026 Westwick-Farrow Pty Ltd