Semiconductor protection tips for 3-level topologies

Supplied by Semikron Pty Ltd on Monday, 21 October, 2019


3-level topologies are mainly used in UPS and solar applications due to their high efficiency and low harmonic distortion of the grid. Essential for the design of the driver is to limit the voltage at the IGBT and handling of short circuits.

This application note describes the control and protection of power semiconductors in 3-level NPC and TNPC topologies.

Related White Papers

Your guide to DC-DC convertor module design

This design guide provides power system designers with detailed insight to best use ChiP DCMs in...

How to fast-track the development of your electronic products

This white paper describes how the TestOps development culture can speed the overall...

Hard switching solution for moderate to high switching environments

New compact solutions for device packaging, silicon integration and MOSFET technology work...


  • All content Copyright © 2020 Westwick-Farrow Pty Ltd