New materials bring new reliability issue

Scientific Devices Australia
By
Friday, 04 April, 2003



Semiconductor device reliability can generally be broken into two parts: infant mortality failures and wearout mechanisms.

Infant mortality failures are due to manufacturing defects. The sources of these defects are generally the same as those that cause yield loss, so instrumentation requirements for detecting both are similar.

Wearout failure mechanisms are known physical degradation mechanisms that will eventually cause the device to fail.

For the reliability assurance engineer, the challenge is to ensure the degradation rate is slow enough to minimise the probability the device will fail within some specified 'useful lifetime'.

As semiconductor devices trend towards smaller geometries, denser packing (transistors/cm2), faster speeds and lower power consumption, requirements for the instrumentation used to monitor their reliability will become more severe.

In many cases, technological advances will simply be continuations of existing industry trends, such as the move towards thinner gate oxides.

However, the introduction of new materials into the process will also influence instrumentation requirements.

For most of the industry's history, semiconductor technology has been based on manipulation of silicon, silicon dioxide and aluminium.

As we reach the fundamental limits of these materials, new ones are being developed that will enhance product performance and/or reliability but may also include additional failure mechanisms that must be addressed.

This article looks at some of the new processes/materials likely to be introduced into the semiconductor process soon and discusses the impact of these changes on the process monitoring instrumentation required to ensure product reliability.

Thin oxides

As oxides grow thinner, reliability assurance engineers continue to need a better understanding of the time dependent dielectric breakdown (TDDB) phenomena. As gate oxide thickness approaches mono-layer dimensions, TDDB studies are focusing on subatomic level defects.

Defects in gate oxides are no longer considered 'thin spots' in the gate dielectric, but rather the chemical state of the silicon and oxide atoms in the dielectric. The issue of quasi-breakdown - gates or capacitors that become leaky but do not become shorted - has also become important. As these issues have developed, the value of voltage and current ramp tests long used for gate oxide studies is increasingly limited. Oxides with quasi-breakdown conditions can who sub-picoamp levels of leakage, which would be invisible with many earlier oxide test systems.

At the same time, the defect density required for reasonable yield and low infant mortality defects continues to drop.

Gate oxide defects will always be an important consideration in technology development for several reasons, particularly because of the increasing sensitivity of today's oxide to smaller defects and the simultaneous growth in demand for lower defect density.

As oxides become more sensitive to smaller defects, the ability to characterise these oxides at low fields becomes critical. Small area defects pull relatively little current before the become hard shorts.

This makes them difficult to detect in large test capacitors where trap assisted tunnelling currents can easily exceed the leakage in a small area defect.

Research has shown that a defect that can reduce the oxide thickness by up to 50% in an area equivalent to 10% of the area of a 0.5 x 1.0 µm gate will pull only 7.6 fA of current at 3 V, while trap assisted tunnelling can be up to 1 pA/cm2.

In many cases, such defects are clearly the root cause of gate oxide failure, but the low tunnelling currents make these defects invisible when tested in a large capacitor.

This has led to the use of voltage ramp and constant current tests to identify defects in the oxide only after they have become hard shorts.

These tests generally rely on very high fields to achieve short test times; therefore, they introduce additional uncertainty with respect to the impact of the high fields.

The use of an array of smaller test capacitors with the same area as a single large capacitor makes it possible to detect the very low tunnelling currents of small defects while still maintaining a short test time.

However, this does not address the issue of the changing nature of gate oxide 'defects'.Today's defects are more likely to be a different chemical state of the atoms in the solid than they are to be macroscopic defects like thinning or metal contamination.

This makes detecting an initial low leakage current an insufficient way to gauge the reliability of the semiconductor device. The ageing of the oxide must be studied.

Again, this ageing is more easily studied with low current measurements at lower fields than with higher fields, which cause a catastrophic breakdown.

Figure 1 shows the change in the current/voltage plot as a function of the ageing of the oxide with a short (10 seconds) tunnelling current stress at sequentially higher fields.

This 'Pronin plot' illustrates:

  • The development of defects ('Fowler-Nordheim Walkout' on the right side of the curve);
  • The change in trapped change in the oxide (shift in the '0 current crossing point', the shift from positive to negative current);
  • The change in trap assisted tunnelling current in both directions as a function of time.

These measurements provide a much more sensitive characterisation of the changes in the thin oxide as a function of ageing stress than a voltage to breakdown histogram would.

Characterising small area capacitors makes it possible to determine the inherent characteristics of the oxide. Testing large arrays of these capacitors makes it possible to detect and characterise anomalous point defects.

The small size of these anomalous defects means that the instrumentation used to detect them must provide femtoamp-level current resolution.

Interlevel dielectric

The parasitic capacitance of the interconnect lines has take a dominant role in determining the maximum speed of a semiconductor device.

At the same time, the impact of the interlevel dielectric on device reliability has increased. Speed degradation can be a reliability issue - one that is increasingly dependent on changes in the interlevel dielectric.

Figure 1: Pronin plot of gate oxide capacitor leakage current, voltage swept from 6 to -2 V, 70 Ã… oxide over well, no source or drain implants around capacitor.

Dielectric absorption

Ions and dipoles in a dielectric material can diffuse in the material when it is exposed to an electric field. This movement of charged particles causes a displacement current in the parasitic interconnect capacitors and changes their capacitance.

This change can have a significant impact on the speed of critical nodes in a semiconductor device.

Recent work has shown that a displacement current as low as 15 fA, measured three seconds after a voltage pulse is applied, can indicate a dielectric absorption effect that can cause a 10% change in the parasitic capacitance over 10 years.

The ability to detect this small current greatly limits the instrumentation that can be used to measure this effect.

Femptoamp-level current resolution is required; also, parasitic instrument dielectric absorption must be much lower than was once possible.

The S600 system introduced a picoammeter front-end, per pin design. This design eliminated the dielectric absorption inherent with traditional tester designs that had a standard probe card, switch matrix, cabling from the probe card to the matrix, and more cabling from the measurement instruments to the switch matrix (Figure 2).

Figure 2: Reducing the length of the signal path between the probes and picoammeter input reduces the test's parasitic dielectric absorption effect and allows measuring the dielectric absorption effect on a typical test structure.

k drift

Low k dielectric materials sometimes show a drift in the measured dielectric constant (k) as a function of time and temperature. This drift can affect the speed of the product causing the device to fail at high speed some time in the future.

The degradation in speed is due to chemical changes that occur in some low k dielectrics. The rate of the chemical reaction that causes this degradation in k can be accelerated by high temperatures.

High temperature ageing of a wafer is difficult due to issues with thermal expansion of the probe and hot chuck. However, high temperatures can easily be developed within small test structures using self-heating techniques.

Figure 3 shows an interdigitated metal capacitor on top of a poly resistor. Current is forced through the poly resistor, resulting in joule heating of the poly line. The temperature of the metal lines is measured using the long serpentine metal line on the lower edge of the poly heater. A measurement of the change in resistance of this metal line as current is forced through the poly heater resistor provides the measure of the temperature.

The change in resistance divided by the TCR (thermal co-efficient of resistance) for the metal provides the temperature of the metal lines.

The current through the heater resistor is ramped up until the metal resistor shows a change in resistance equivalent to the desired stress temperature (typically 450-500°C).

The capacitor is aged for some time (typically 30-120 seconds), then allowed to cool to room temperature. The small thermal mass of this test structure allows it to be heated to 500°C in less than one second and to cool to room temperature in less than five seconds. Following the cool down, the change in capacitance of the interdigitated capacitor can be calculated and a change in k computed.

The quantity of current required to drive a self-heated resistor is typically between 150 and 200 mA. This provides the power needed for this technology without exceeding the current limitations of the probes.

Measuring the change in temperature requires instrumentation able to measure a change in resistance of the TCR of the metal (eg, the TCR of Cu is 0.36%/°C, so the instrumentation must be able to resolve a 0.36% change in resistance).

This measurement is complicated by the fact that the metal line usually has low resistance and the current that can be forced through it must be less than that which will cause joule heating.

For a metal line 0.2 µm wide and 200 µm long with a sheet resistivity of 0.05 ohms sitting on 2 mm of oxide with a thermal resistance of 0.022°C/watt/µm/cm2, the maximum voltage drop across the metal thermometer would be 11 mV.

Therefore, the instrumentation resolution required to measure a change in temperature of the line with 1°C resolution is 0.36% of 11 mV or 40 µV.

The size of the capacitor is limited by the fact that the current that can be forced through one probe needle is limited.

While multiple probe pads could be connected to one self-heated resistor, this greatly increases the silicon area required to make this measurement.

Limiting the current limits the width of the self-heated resistor because a certain power density is required to reach any specified temperature.

If the test structure is designed to fit into a typical scribe lane and the heater current is limited to the level that can be safely forced through a single probe needle, then the capacitance of the test structure will be very limited.

The capacitance of an interdigitated capacitor with 1500 µm of perimeter, a space of 0.2 µm, a metal line thickness of 0.5 µm and a k of 3.0 would produce a capacitance of about 100 fF.

If the ability to resolve a 1% shift in this parameter is desired, the instrumentation must be able to resolve a 1 fF shift in the measured capacitance.

Copper metal issues

The drive to reduce the parasitic RC delay associated with the metal interconnect lines has led the industry to move away from the traditional aluminium interconnect metal lines in favour of copper-based metallisation.

The sheet resistivity of Cu-based metal lines can be half that of A1-based metal systems. However, the move to Cu will require new process steps and has some new reliability risks associated with it.

Copper diffuses into SiO2

Cu diffuses easily into SiO2 at normal processing temperatures, which increases the metal resistivity and decreases the isolation between adjacent metal lines.

To prevent this, most Cu processes (eg, dual damascene process) add a refractory barrier metal layer (eg, Ta, W, or TaN), which is more resistive than A1, between the Cu and any SiO2. For very narrow Cu lines, this can be a very important issue.

Thick barrier layers can result in metal line resistance that is higher than A1 lines. Therefore, the thickness of the barrier layer must be minimised.

At the same time, cracks or holes in the barrier layer will allow the Cu to diffuse into the adjacent dielectric material and may cause leakage.

This is the sort of 'narrow process window' that requires careful process control to provide high-speed performance without the generation of a few defects in every 10,000 devices (10 FIT reliability).

Defects in the barrier layer can be most easily detected through leakage between minimum spaced metal lines. If the space between metal lines is 0.2 mm, and the same interdigitated capacitor is used as described in the previous example, then the area of the sidewall capacitor will be 750 µm2.

If an electric field of 7.5 MV/cm (150 V) is applied across this dielectric, the Fowler-Nordheim leakage current will be about 3.7 x 10-16 A (0.37 fA).

However, if there were a defect that allowed the dielectric thickness to be reduced by 50% in an area of 2 µm2, the leakage current through the defect would be 72 pA.

Thus, the instrumentation should be able to generate a voltage sufficient to produce an electric field of at least 7.5 MV/cm across the minimum metal space. If defects smaller than a defect which will reduce the equivalent oxide thickness by 50% must be detected, then the current sensitivity must be greater than the 72 pA value shown in the example, or the forced electric field must be increased.

The ability to detect a 25% defect at 150 V would require the ability to resolve a leakage of 7.5 fA in a defect with an area of 2 µm2.

Cu electromigration

Initial results of electromigration testing on Cu metal lines indicate that the rate of change of the resistance of the Cu metal line under an electromigration stress will be about one-tenth the rate of change of a similarly stressed A1 line.

This has led to a belief that Cu is inherently less sensitive to electromigration failure than similarly stressed A1 lines. However, Cu does have one area of sensitivity not seen in A1-based technology.

In the damascene process, the Cu is electroplated into refractory metal lined trenches, then coated with a thin silicon nitride layer. The adhesion of the Cu to the silicon nitride is not strong.

When electromigration occurs in a metal line, metal atoms tend to accumulate at the positively biased end of the line. This accumulation generates a compressive stress in the metal line that is proportional to the current density.

If the line under stress is wide and is separated by a minimum space from another wide Cu line, a significant tensile stress is wide and is separated by a minimum space from another wide Cu line, a significant tensile stress is transferred to the small oxide layer separating the two lines.

This can lead to the silicon nitride delaminating from the oxide between the metal lines and result in a short between the two metal lines.

Early testing of Cu electromigration has reported a significant rate of failure due to adjacent shorts. Electromigration test results can be confounded by the thermal expansion of the metal at high stress temperatures and by the fact that the ultimate stress generated in a metal line is a function of the stress current density.

Therefore, highly accelerated electromigration tests can result in pessimistic predictions of interlevel oxide failures if the ultimate stress achieved by the use condition stress is less than the fracture strength of the oxide.

This relationship has not been fully explored at this point. However, the possibility does exist for electromigration stress induced failure of the sidewall dielectric.

Declining mechanical strength associated with some low k dielectric materials may increase the frequency of such fractures.

The strength of the sidewall oxide can be tested quickly using joule heating. The thermal expansion co-efficient of Cu is 16.2 ppm/°C. The thermal expansion co-efficient of SiO2 is close to 0.3 ppm/°C.

Heating the line by forcing a high current through it causes it to expand and produces tensile stress in the surrounding oxide layers in a manner similar to that accomplished using the accelerated electromigration tests.

The temperature of a line can be measured by the change in resistance of that line. The stress generated by the heating of the line can be calculated from the dimensions and the temperature change.

A fast current ramp with a consistent measure of the line resistance/temperature, accompanied by the ability to detect leakage to an adjacent metal line, can be used to measure the strength of the sidewall dielectric. This can be an important process control variable for Cu metallisation.

The instrumentation required to perform this test must be able to supply a significant current density in the line.

Joule heating of 100°C in a 5 µm (wider lines mean more stress) Cu metal line with a sheet resistivity of 0.025 ohms sitting on 0.5 µm of oxide with a thermal resistance of 0.022°C/Watt/µm/cm2 will require a current of slightly less than 300 mA.

A current of about 360 mA will be required to raise the temperature by 200°C. (Keep in mind that the line resistance will increase as the line temperature increases, causing greater power dissipation.)

This measurement will require multiple probe pads for the forced current, but will be able to provide a measure of the strength of the sidewall oxide in a matter of a few seconds. The instrumentation required to conduct this measurement must be able to source at least half an amp and to measure voltage with a resolution of at least 1 mV.

Conclusions

The instrumentation required to assess the reliability of state-of-the-art semiconductor technology must provide better performance than the instruments used even a few years ago. As we approach the fundamental limits of the materials used to build devices, the process box that will allow building reliable material becomes ever tighter. Controlling 0.18 to 0.1 µm processes will demand the ability to measure currents of 1 fA or lower to create reliable gate dielectrics and interlevel dielectric layers.

Additionally, modern instrumentation must reduce the parasitic dielectric absorption effects due to the instrumentation itself.

The development of lower resistivity materials such as Cu will require higher current source capability. Currents in the range of 0.5-1 A will be useful for characterising the reliability of the Cu material and the interaction between the Cu and the interlevel dielectric layers.

The interaction between Cu and SiO2 creates a demand for high voltage capability.

A voltage of at least 150 V is required for 0.18 µm processes. Lower voltages will be acceptable as the geometries continue to decrease.

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