Chip stacking technique boosts semiconductor performance

Researchers from the Pohang University of Science and Technology (POSTECH) have developed a technology that enables the stable stacking of more than 10 ultrathin semiconductor chips, each only one-fifth the thickness of a human hair.

Led by Professor Seok Kim and PhD student Uhyeon Kim, the researchers achieved an integration density approximately four times higher than that of commercial high-bandwidth memory (HBM) through a novel process that simultaneously transfers chips and forms metallic interconnections. The research findings have been published in the journal Results in Engineering.

AI services such as ChatGPT, image-generation AI and autonomous vehicles all process enormous amounts of data at high speeds. While electronic devices become thinner, semiconductor performance continues to improve because chips are no longer expanded laterally but stacked vertically. This is analogous to constructing high-rise apartment buildings instead of single-family homes when urban land becomes scarce. High-Bandwidth Memory (HBM), a key technology that determines the performance of AI accelerators, is built by vertically stacking multiple memory chips, making the ability to reliably stack a large number of chips a critical challenge.

The difficulty lies in handling ultrathin chips; as chip thickness decreases below several tens of micrometres (μm), chips become increasingly susceptible to bending, warping and fracture. This challenge becomes more severe as the number of stacked layers increases.

Conventional semiconductor packaging processes primarily rely on flip-chip bonding and carrier-wafter-based grinding processes. However, flip-chip bonding requires precise pneumatic nozzle design and process control, while grinding-based approaches often suffer from handling damage and warpage. These issues become more pronounced when chip thickness falls below several tens of micrometres.

To address these limitations, the researchers leveraged the inherent stability of transfer printing technology, demonstrating both reliable integration and the fabrication of chips with thicknesses in the 10-micrometre range.

The team combined two technologies into a single process platform: Transfer Printing, which precisely places chips at desired locations, and In-situ Bonding, which forms metallic bonds simultaneously during chip transfer. This integrated approach allows chip transfer, placement and electrical interconnection to be completed in a single process.

To validate the new process, the researchers fabricated ultrathin silicon chips approximately 14 μm thick. Each chip incorporated both vertical electrical signal pathways and lateral redistribution wiring, making the structure suitable for multilayer integration.

Using the developed process, the team successfully stacked more than 10 ultrathin chips under low-temperature (below 180°C) and low-pressure (below 20 kPa) conditions. Even after repeated stacking, interlayer alignment errors remained extremely small, and structural warpage was significantly suppressed. The achieved integration density — defined as the number of stacked layers relative to total package thickness — was approximately four times greater than that of conventional 12-layer HBM structures. In other words, substantially more chips can be accommodated within the same vertical height.

Commercialisation of this technology could increase the number of chips integrated within a given space, enabling significant improvements in AI semiconductor performance. Furthermore, the technology has potential applications beyond memory devices, including chiplet-based heterogeneous integration and next-generation micro-LED displays, suggesting a broad technological impact.

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